Lean, informalized

Nielsen & Chuang · Chapter 10, Quantum error-correction · p. 491

Exercise 10.69 - Faults in preparing and verifying a cat state ancilla, and the bit flips they leave behind

A single fault leaves at most one bit flip.

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The Exercise

An ancilla is prepared in a cat state on a block of qubits and verified before it is used. The verification copies the parity of two qubits of the block onto a check qubit, with a controlled NOT (CNOT) from the first of them onto it followed by a CNOT from the second.✦ The exercise asks to show that a single fault anywhere in the preparation or the verification either shows up in a parity check or leaves at most one bit flip on the ancilla.✦

The library takes a single fault to be a set of bit flips, either on the qubits of the prepared cat state or on the qubits of the verification at one moment of it.

Qubits and Gates

A quantum system SS is a physical system whose state space is a finite dimensional complex Hilbert space✦, and a pure state ψ\psi of SS is a unit vector in that space, ‖ψ‖=1\lVert \psi \rVert = 1.✦ The qubit is the system with state space ℂ2\mathbb{C}^2✦; its basis states |0⟩|0\rangle and |1⟩|1\rangle are the standard basis vectors.✦ The composite system S⊗TS \otimes T of two systems SS and TT has the tensor product of their state spaces as its state space.✦

A unitary UU of SS is an operator on the state space of SS with U†U=UU†=1U^\dagger U = U U^\dagger = 1✦, and it carries a pure state ψ\psi of SS to the pure state UψU\psi.✦ Of two unitaries UU and VV of SS, the unitary UVUV applies first VV and then UU✦; the identity evolution 11 is the unitary whose operator is the identity.✦ Unitaries UU of SS and VV of TT give the product unitary U⊗VU \otimes V of S⊗TS \otimes T, the tensor product of the two operators✦, and 1⊗V1 \otimes V is the gate VV acting on the second factor and leaving the first alone.

The Pauli XX is the unitary of the qubit with the matrix below✦, and for a unitary UU of a system SS the controlled gate C(U)C(U) is the unitary of qubit⊗S\mathrm{qubit} \otimes S that applies UU to SS when the control qubit is |1⟩|1\rangle and the identity when it is |0⟩|0\rangle: X=(0110),C(U)=|0⟩⟨0|⊗1+|1⟩⟨1|⊗U.X = \begin{pmatrix} 0 & 1 \\ 1 & 0 \end{pmatrix}, \qquad C(U) = |0\rangle\langle 0| \otimes 1 + |1\rangle\langle 1| \otimes U .(1)✦ The CNOT gate is the unitary C(X)C(X) of two qubits.✦

The Cat State

The bit register over a finite set ι\iota is the system of qubits labelled by ι\iota; its state space is ℂ[ℤ2ι]\mathbb{C}[\mathbb{Z}_2^{\iota}], with an orthonormal computational basis {|w⟩}\{|w\rangle\}, one vector for each bit vector w∈ℤ2ιw \in \mathbb{Z}_2^{\iota}.✦ For bit vectors vv and uu over ι\iota, the bit flip string XvX^v, the unitary that flips the qubits where vv is one, and the phase flip string ZuZ^u act on the basis as Xv|w⟩=|w+v⟩,Zu|w⟩=(−1)u⋅w|w⟩.X^v |w\rangle = |w + v\rangle, \qquad Z^u |w\rangle = (-1)^{u \cdot w} |w\rangle .(2)✦

An observable AA on a system SS is a self adjoint operator on its state space, A†=AA^\dagger = A✦, and a pure state ψ\psi of SS is an eigenstate of AA with eigenvalue μ∈ℝ\mu \in \mathbb{R} when A|ψ⟩=μ|ψ⟩A|\psi\rangle = \mu|\psi\rangle.✦ For i,j∈ιi, j \in \iota, the parity ZiZjZ_iZ_j is the phase flip string ZuZ^u of (2) with uu the sum of the bit vectors that have a single one, at ii and at jj: a Hermitian unitary, taken as an observable.✦

For a finite set ι\iota, the cat vector of the bit register over ι\iota is the vector |0⋯0⟩+|1⋯1⟩|0\cdots0\rangle + |1\cdots1\rangle of its state space, the sum of the basis vectors of the all zero and the all one bit vectors.✦ For nonempty ι\iota, the cat state |cat⟩|\mathrm{cat}\rangle of the register over ι\iota is the pure state obtained by dividing the cat vector by its norm, |cat⟩=12(|0⋯0⟩+|1⋯1⟩).|\mathrm{cat}\rangle = \tfrac{1}{\sqrt{2}} \bigl( |0\cdots0\rangle + |1\cdots1\rangle \bigr) .(3)✦

The Verification Gadget

The gadget acts on the three qubit register qubit⊗(qubit⊗qubit)\mathrm{qubit} \otimes (\mathrm{qubit} \otimes \mathrm{qubit}), whose qubits are numbered 00, 11 and 22, the last in the role of the check qubit. The gate CNOT02\mathrm{CNOT}_{02} is the controlled gate C(1⊗X)C(1 \otimes X), with qubit 00 as control and the Pauli XX on qubit 22✦, and CNOT12=1⊗CNOT\mathrm{CNOT}_{12} = 1 \otimes \mathrm{CNOT} is the CNOT gate on the last two qubits. The verification gadget applies the first and then the second, G=CNOT12CNOT02.G = \mathrm{CNOT}_{12} \, \mathrm{CNOT}_{02} .(4)✦

For a bit aa, the flip XaX^a selected by aa is the identity for a=0a = 0 and the Pauli XX for a=1a = 1.✦ A pattern e=(e0,e1,e2)e = (e_0, e_1, e_2) of three bits gives the unitary Xe=Xe0⊗Xe1⊗Xe2X^e = X^{e_0} \otimes X^{e_1} \otimes X^{e_2} of the register✦, and a fault is such a pattern striking at one of three time slices ss of the gadget, which sit around the two CNOTs as input→CNOT02→between→CNOT12→output.\text{input} \;\longrightarrow\; \mathrm{CNOT}_{02} \;\longrightarrow\; \text{between} \;\longrightarrow\; \mathrm{CNOT}_{12} \;\longrightarrow\; \text{output} .(5)✦ The gadget with the fault ee at the slice ss is the unitary Gs(e)={GXe,s=input,CNOT12XeCNOT02,s=between,XeG,s=output.G_s(e) = \begin{cases} G \, X^e, & s = \text{input}, \\ \mathrm{CNOT}_{12} \, X^e \, \mathrm{CNOT}_{02}, & s = \text{between}, \\ X^e \, G, & s = \text{output}. \end{cases}(6)✦

The Claim

Theorem 1. Let ι\iota be a finite nonempty set and pp a bit vector over ι\iota, and let ee be a pattern of flips at a time slice ss of the gadget that flips at most one of qubits 00 and 11, e0+e1≤1e_0 + e_1 \le 1. Then ZiZjXp|cat⟩=−Xp|cat⟩ for some i,j∈ι,orXp|cat⟩=Xr|cat⟩ for some bit vector r of weight ∑iri≤1;Gs(e)=XfG for some pattern f with f0+f1≤1.\begin{gathered} Z_iZ_j \, X^p|\mathrm{cat}\rangle = -X^p|\mathrm{cat}\rangle \ \text{ for some } i, j \in \iota, \quad \text{or} \\ X^p|\mathrm{cat}\rangle = X^r|\mathrm{cat}\rangle \ \text{ for some bit vector } r \text{ of weight } \textstyle\sum_i r_i \le 1 ; \\ G_s(e) = X^f \, G \ \text{ for some pattern } f \text{ with } f_0 + f_1 \le 1 . \end{gathered}(7)✦

What Is Checked

The claim is stated over the cat state (3) of the register over ι\iota, the bit flip strings applied to it and the parities ZiZjZ_iZ_j, and over the gadget (4), its time slices (5) and the faulty gadgets (6) built from the patterns XeX^e.

About these constructions the library proves that the cat vector is nonzero, so that it can be normalized✦, and that the controlled gate C(U)C(U) is unitary for every unitary UU, the CNOT gate and CNOT02\mathrm{CNOT}_{02} among them.✦ Products and tensor products of unitaries are unitary as well, so GG, the patterns XeX^e and every Gs(e)G_s(e) are unitaries of the three qubit register.